Specialist LCD/OLED Supplier

This article is a tutorial to drive LCD AT043TN24, the developers can take it as reference.
Related: AT043TN24 LCD parameters

1. LCD type, Circuit connection, Display principle

Circuit Module


Controller Schematic Diagram

Display Principle

In addition to configuring some registers to tell the LCD controller the format of the pixels in the image (RGB565), the initial address of the frameBuffer, and so on, Some signals are needed to access TFT LCD, so it is necessary to configure registers to tell the LCD controller the information of these signals (such as when to send the control signal, the duration of sending the signal, etc.). For example, When sending picture data to LCD driver, clock control (VCLK) is needed. A clock sends a pixel, then the controller needs to actively send a clock signal, which pin is sent by the clock, and what is  the frequency, these are need to be configured. We analyze some signals needed and how to configure them through the sequence diagram. It is difficult to see the sequence directly if you know LCD control for the first time, so just give a visual metaphor first.



Frame Buffer: The frame buffer is used to store LCD data. frame buffer establishes one-to-one mapping relationship between LCD controller and LCD Panel.
LCD controller: Refer to the LCD user manual to configure the LCD controller, which is used to send LCD control signals and drive the LCD display.
Scanning mode: As shown in the figure, the scanning direction from start to end is: from left to right, from top to bottom (one kind of scanning direction);
HSYNC: Line synchronization signal, which is used for line switching. When a line scan is complete and a new line needs to be scanned, the line synchronization signal needs to be sent first.
VSYNC: Column synchronization signal, used for column switching. When a frame scanning is finished and a new frame needs to be scanned, the column synchronization signal needs to be sent first.
Clock signal: Each time a clock comes, the scanning point shifts one.

In the image above, the LCD driver can be likened to the electron gun, which is controlled by the LCD controller. It takes pixel data from the display cache to the electron gun and sends the command to the electron gun to emit pixel colors

a. The LCD controller sends a VSYNC signal to tell the electron gun that a new frame is coming out, and the electron gun turns the gun to the top left corner of the LCD screen, ready to start firing pixels.
b.  At the same time as the VSYNC signal, the HSYNC signal (telling the gun to start a new line, move from left to right to fire the bullet) is issued, but the gun is slow to react and starts firing after a few seconds. For the above two processes, as the electron gun received the VSYNC signal, it would take some time to react before it could work normally after turning the gun head, so several lines of invalid data were shot for nothing, which is equivalent to several HSYNC signal cycles. An HSYNC cycle is the time it takes the gun to sweep a row (the time it takes from the beginning of the HSYNC signal to the end of the first row until the end of the row), and the upper void zone appears.
c.  When the first row ends, the LCD controller sends out HSYNC signal again, and the electron gun head twists to the next row and starts transmitting data, but the gun head twists slowly, so there is invalid area left and right (that is, after the end of the first row, the electron gun has to react for some time due to hardware reasons, so there is invalid data area on the right.  After turning the gun head, it have to react for a while and start firing bullets, so LCD have this dead zone on the left）Some people will ask how the electron gun knows when the first row is over, actually we tell the LCD controller how many data are in the first row through the register, our screen resolution is 480*272, it will be settled  into the regiester.)  When a row is over, the LCD controller stops sending valid pixel data and waits for the gun to drift away for a while before sending the HSYNC signal for the next row.
d. Loop c step
e. When the scan reaches the end of the last line (a frame is about to end), the LCD controller will no longer send valid pixel data and wait for the electron gun to drift away for a period of time, so it will continue to scan down and the lower invalid area appears. After that, it will send the VSYNC signal of the next line, and then return to process 1 step and start to repeat.

On a working monitor, you can see a black border around it. The black borer at the top is because, when sending a VSYNC signal, it takes several rows for the first row to be valid; The black border at the bottom is because, when all lines of data are displayed, the display has not scanned to the bottom (the VSYNC signal has not been sent), then the data is invalid; The black border on the left is because when the HSYNC signal is sent, it takes several pixels for the first column of data to be valid; The black border on the right is because when a line of data is displayed, the display has not yet scanned to the far right (HSYNC signal has not been sent), and the data is invalid. The display screen only obtains and displays data according to VSYNC and HSYNC signals, regardless of whether the data is valid. The video card or LCD controller decides when to send valid data.


The frequency at which the VSYNC signal appears indicates how many frames can be displayed in a second. This is called the vertical frequency or field frequency, which is often referred to as the "display frequency". The frequency at which the HSYNC signal appears is called the horizontal frequency, which indicates how many pixels of data can be displayed per second.

On the monitor, the relationship between the storage location of a frame of data and VSYNC and HSYNC signals is shown in the figure below，


The number of rows and columns of valid data, that is, the resolution, the distance between it and VSYNC, HSYNC signal, etc., can be set, which is completed by the LCD controller.

Data Organization Mode

An image is called a frame. Each frame is composed of multiple lines, each line is composed of multiple pixels, and the color of each pixel is represented by several bits of data. For monochrome displays, each pixel is represented by 1 bit, called 1BPP; For 256-color displays, each pixel is represented by 8 bits, known as 8BPP.

The color of each pixel on the display consists of three parts: Red, Green, and Blue. They are called the three primary colors, and a mixture of the three represents almost all the colors that the human eye can recognize. For example, the three primary colors can be divided into 256 levels according to the depth of the color, then you can use 255 level red, 255 level green, 255 level blue combination into white, or use 0 level red, 0 level green, 0 level blue combination into black.

LCD controller can support monochrome (1BPP), 4-level gray (2BPP), 16-level gray (4BPP), 256 color (8BPP) palette display mode, support 64K(16BPP) and 16M(24BPP) non-palette display mode. The following introduces 64K(16BPP) color display mode, image data storage format.

How Image Store As Data

The 64K(16BPP) color display mode uses 16 bits of data to represent the color of a pixel. The 16-bit data format is divided into two types: 5:6:5 and 5:5:5:1. The 5:6:5 mode uses the front 5 bits to represent red, the middle 6 bits to represent green, and the last 5 bits to represent blue. The 5:5:5:1 mode's front 15 is divided into three five digits from high to low to represent red, green and blue, and the last digit represents transparency. The 5:5:5:1 format is also known as the RGBA format (A:Alpha, for transparency).

A 4-byte data can represent two 16BPP pixels, and it is optional to use the front or last 2 bytes to represent the first pixel. When the display mode is 16BPP, the relationship between memory data and pixel position is as follows,

a.When BSWP=0 and HWSWP=0, the memory pixel arrangement format is as follows，

Pixel arrangement on the LCD screen

Mapping between plain color value and VD[23:0] pin

The Image Output Mode

a. Display with a frame buffer (most typically)



As we see in the figure above, we need to apply for a block of memory in the memory (this memory is called frame buffer), and then configure the LCD controller.
Tell the controller the first address of the frame buffer, and the controller takes the pixel values from the frame buffer and shoots different colors at the LCD screen based on the pixel values. LCD controllers are similar to electron guns,
The LCD controller has a DMA channel inside it. For the frameBuffer, each value corresponds to one pixel of the LCD screen.

As shown in the figure above, the LCD screen resolution is (480*272). We can define an array with the size of array a[272][480] and tell the LCD controller the address of the array at the beginning.

Then each item of the array corresponds to a pixel of the LCD screen. For example, if a[0][0] is assigned 0xFFE0, the first pixel of the corresponding LCD screen is displayed as yellow.

b. Display Through A Temporary Color Palette

Tips
What Is A Temporary Color Palette
This register value will be video data at next frame.  (Tips: One image per frame.)
The temporary color palette is a register, we write the color into this register, then the LCD screen will display the next image is the color recorded in this register, that is, it plays the role of brushing the screen (the whole screen is one color).

When Does It Work And What Does It Do
When this register is enabled, the temporary palette takes effect, and previously configured functions such as display through the frame buffer are invalid, because the LCD screen will be brushed quickly. To achieve this, you do not need to use SDRAM to assign the same value to all elements of the frameBuffer. (tips: With SDRAM, it is already slow). So if you want to restore the previous configuration, disable the Temporary palette function.

c.  Display Through The Color Palette

In the image above, the palette is a block of memory inside the controller (note the difference between the temporary palette). The initial address is 0x4D00400 and there are 256 2-byte sizes (each two bytes represents a color). In the image above, the configuration register tells the LCD controller that the format of the palette is RGB565. The palette then needs to be assigned manually, such as the position in Figure 00H as "yellow". Then, for the framebuffer, each entry represents an index in the palette, such as the first entry of the frameBuffer having a value of 0, The hardware automatically finds the value of the first item in the palette, which is 0xFFE0, and the LCD displays yellow on the first pixel
One more question, how do I enable the color palette? As we mentioned in "Display by frame buffer" above, configuring the register to display 16BPP at 5:6:5 means that the controller assumes that each element in the frame buffer represents a color value and displays it at 5:6:5. But if we set the display mode to 8BPP and the display mode is 5:6:5, the LCD controller automatically assumes that the palette mode is used and the colors in the palette are displayed as (5:6:5). (8Bpp here means that each element in the frame buffer is represented in 8-bit binary notation. The value of each element is the index value in the palette), so what is the application of the palette?
Let` take a 640x480 LCD as example, If the color depth is set to 16 bpp, the picture will appear obvious jitter and incoherence when the system is in use, which is caused by the excessive computing load of the chip. If the palette method mentioned in this paper is adopted, that is, 8-bit color depth display, the selection of colors can meet the needs, and the display of the picture will be obviously stable. This shows that the color palette technology is a very important choice in embedded applications with high display resolution and simple color types.


TFT-LCD Timing

Each VSYNC signal represents the beginning of a frame of data; Each HSYNC signal indicates the start of a row of data, whether it is valid or not; Each VCLK signal indicates that one pixel of data is being transmitted, whether it is valid or not. The data is valid only for the CPU's LCD controller, which reads and displays the bus data continuously according to VSYNC, HSYNC, and VCLK.


a. Corresponding to the above process 1,2, the VSYNC signal (representing the beginning of a frame) needs to be sustained for a period of time ②(VSPW+1). The electron gun thinks that the VSYNC signal has been received (i.e. the white strafed VSPW+1 line, It can also be said that the white stringer (VSPW+1) HSYNC cycle time), after receiving the signal, but also continue the duration of ③(VBPD+1), the LCD controller began to send effective data, so that the electron gun emission effective pixels, namely (② + ③) for the LCD screen above the invalid area, for ① parameter, This is the data in the manual, which tells us that the default LCD controller sends HSYNC signal as high level, but the actual LCD accepts HSYNC hardware may be designed as low level effective, so you can modify the register so that the LCD controller sends HSYNC control signal as low level.

b. ④ is valid data the (LINEVAL + 1) row, and this LCD resolution is 480 * 272, so the LINEVAL is 271 *

c.⑤ VFPD + 1 parameter corresponds to the step 5, when scanning to the end of the last line (i. e., a frame ended), the LCD controller will not send valid pixel data, the electronic gun will stop sending for a period of time, will continue to sweep several lines (VFPD + 1 line) invalid data. LCD controller need to know this time, so that the controller know how long to wait to send VSYNC signal, to start the next frame.

d.For the three parameters, ⑥, ⑦, ⑧, and ⑩, Corresponding to the above-mentioned step 3. After receiving the HSYNC signal (indicating the beginning of a line), this signal must last for a period of ⑦ (HSPW + 1 VCLK cycle), then the electron gun thinks the signal is valid.

After receiving the HSYNC signal, the electron gun also reacts with ⑧ for a period of time (after sweeping HBPD + 1 VCLK cycle, Or, after launching HBPD + 1 invalid pixel), The LCD controller only begins to transmit valid data to the electronic gun, When a line of scan is finished, That is, the LCD controller does not emit valid data, At this point, the electron gun to free for a period of time ⑩ (HFPB + 1), This is time time to tell the LCD controller, To allow the LCD controller to wait to send the HSYNC signal to scan the next line, For the ⑨ parameter, A resolution of 480 * 272, So that HOZVAL = 479, That is, a row has 480 valid data. Note the timing of valid data,after the time (⑦, ⑧), The LCD controller only starts sending valid data.

Parameter Calculation

According to the values of the above parameters confirmed by LCD datasheet, the following figure is the timing diagram of the AT043TN24 data manual, and we can easily correspond to the parameters in the timing diagram of the LCD in the 2440 manual above

The VSYNC and HSYNC pulse generation depends on the confgurations of both the HOZVAL field and the LINEVAL field in the LCDCON 2/3 registers. The HOZVAL and LINEVAL can be determined by the size of the LCD panel according to the following equations:
--- HOZVAL = (Horizontal display size) -1
--- LINEVAL= (Vertical display size) -1

As we can see, on the left side of the figure above are the specific parameter values, Min, Typ, Max, For example, In the right figure, we know that "VSPW + 1 = tvp", a typical value of tvp in the left figure is 10, in the units of H (Hsync), so VSPW + 1 = 10==> VSPW = 9, The values of the remaining parameters can be determined by the above method, There is also a question left out here, Time of the VSPW, VSPD, VFBD are all dependent on the HSYNC cycle time, so how to confirm the HSYNC cycle time? We can found this sentence in the 2440 manua.


In fact, it means that the LCD controller will confirm the HSYNC time according to the number of pixels emitted by the electronic gun. For example, our LCD screen resolution is 480 * 272. When the VSYNC signal is sent, it will pass the VSPW + 1 reaction time, namely VSPW + 1 HSYNC cycle. We assume that the value of "VSPW + 1" is 10, then it`s 10 HSYNC cycles, that is, after the electronic gun scans 10 x 480 pixels, the LCD controller will experience 10 HSYNC cycle time.

1、VCLK(Hz) = HCLK/[(CLKVAL+1)*2]
2、VSYNC =1/[ {(VSPW+1)+(VBPD+1)+(LIINEVAL+1)+(VFPD+1)} x {(HSPW+1)+(HBPD+1)+(HFPD+1)+(HOZVAL+1)} x {2x (CLKVAL+1) / (HCLK )} ]
3、HSYNC = 1/[{(HSPW+1)+(HBPD+1)+(HFPD+1)+(HOZVAL+1)} x {2x (CLKVAL+1) / (HCLK )}]



After setting the time parameters of VSYNC, HSYNC, VCLK and other signals, and telling the address of the frame memory to the LCD controller, it can automatically issue DMA transmission to get the image data from the frame memory, and finally appear on the data bus VD [23:0] under the control of the above signal. The user only needs to write the image data to the frame memory.

2. LCD Controller REGBANK Register Group

2.2 The LCD Control Register LCDCON2

Time parameters is for setting  each signal in the vertical direction, the format is shown in the following table,

2.3 The LCD Control Register LCDCON3

It`s used to settle time parameters for each signal in the horizontal direction in the format shown in the following figure,

2.4 The LCD Control Register LCDCON4

For TFT-LCD, this register is only used to set the pulse width of the HSYNC signal, the value [7:0] is called HSPW, representing the pulse width bit (HSPW + 1) VCLK period.


2.5 The LCD Control Register LCDCON5

It`s to set the polarity of each control signal and reads some status information in the format shown in the following table,

2.6 Frame Memory Address Register LCDSDRR1~LCDSDRR3

The frame memory can be large, and the real area to be displayed is called the "viewport" , which is within the frame memory. These three registers are used to determine the starting address of the frame memory and locate the position of the viewport in the frame memory.
The following figure shows the positional relationship between the frame memory and the viewports,




The following figure introduces each frame memory register,

LCDSADRR1 register format

LCDSADRR2 register format

Note: The values of LCDBASEU and LCDBASEL can be modified to move the image, but it cannot be modified at the end of a frame image.



LCDSADRR3 register format

3. Color Palette

Temporary Color Palette Register TPAL

If you want to output a monochrome image, you can set this color value in the TPL register and then enable the TPAL register, which can avoid modifying the entire palette or frame buffer.

TPAL Register Format

4. Write The Driver Program

Set the fixed parameter —— fb_fix_screeninfo structure

Set Variable Parameters

Hardware-Related Operations

Configure the GPIO for the LCD

                                                                           LCD Interface socket



                                                             LED backlight driver circuit


According to the schematic diagram, all the used pins are to be configured. Then view the schematic diagram and find the IO port corresponding to each pin,

Then, define a pointer to a structure of that type, 'lcd_regs' :

static volatile struct lcd_regs* lcd_regs; // All addresses to registers must be volatile

Finally, perform the address mapping in the 'lcd.c' function, and then set the LCD control register according to the LCD data manual,



LCD Time Paremeters



LCD Time Series

Register

5. Compilation And Testing 

6. Modify the kernel comes with an lcd drive to support a 4.3-inch (480X272) screen